In semiconductor or integrated circuit manufacturing, large scale integration (LSI) or very large scale integration (VLSI) techniques may be used to fabricate complex electrical circuits on a silicon substrate. The design and manufacture of many devices have been made possible by the reduction in the memory cell dimensions. A photolithography step is frequently utilized to transfer an electrical pattern from a photomask to a silicon wafer. Various photolithographic systems use a variety of transfer techniques, including step-and-repeat processes, to gradually transfer a mask pattern from a macroscopic prototype to a microscopic implementation.
As device memory cell dimensions continue to shrink, the overlay measurement accuracy (to compensate for processing inaccuracies) generally requires alignment marks to be created in the silicon substrate to be used as a reference coordinate. The alignment marks are created by various processing steps. Global alignments between masking layers are generally done by measuring contrasts in light intensities reflected back from the steps created by the elevated portions of the alignment marks. Generally, as long as the step heights in the alignment marks are preserved through subsequent processing steps, global alignment in masking steps (compared to the masking layers) can be achieved. As critical dimensions (CD) of individual transistors transferred from a mask pattern shrink in extremely dense devices, global planarization at the wafer level therefore becomes quite advantageous.
Chemical Mechanical Polishing (CMP) is an industry recognized process for making silicon wafers flat. The CMP process is used to achieve global planarization (planarization of the entire wafer). Both chemical and mechanical forces produce the desired polishing of the wafer. The CMP process generally includes an automated rotating polishing platen and a wafer holder. The wafer holder is generally used to hold the wafer in place while the platen exerts a force on the wafer. At the same time, the wafer and platen may be independently rotated. A polishing slurry feeding system may be implemented to wet the polishing pad and the wafer. The polishing pad bridges over relatively low spots on the wafer, thus removing material from the relatively high spots on the wafer. Planarization occurs because generally high spots on the wafer polish faster than low spots on the wafer. Thus, the relatively high portions of the wafer are smoothed to a uniform level faster than the other, relatively low portions of the wafer.
After CMP, the various portions of the wafer, including the alignment marks, become relatively flat. Planarizing the alignment marks creates problems for providing proper alignment during subsequent masking steps.
One typical way to get around planarizing the alignment marks is to perform a processing step called "open frame" which reproduces the step height in the alignment marks.
Tungsten deposition and CMP are typically used to fabricate tungsten contacts. Thus, Tungsten CMP (WCMP) is one notable variation of CMP. Tungsten is generally preferred to aluminum for contacts due to step coverage problems that arise in high aspect ratio holes during aluminum deposition. After tungsten CMP, the original alignment marks may be covered with a layer of tungsten film. The grain quality of the tungsten film typically produces poor light reflection quality and therefore makes alignment of the mask pattern difficult to control. As a result, alignment marks may be rendered ineffective after tungsten CMP.